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1 lcc top view 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 a12 a7 a6 a5 nc nc nc a4 a3 a2 a1 a13 a8 a9 a11 nc nc nc nc oe a10 ce 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 a0 i/o0 i/o1 i/o2 vss nc i/o3 i/o4 i/o5 i/o6 i/o7 a15 a16 a18 nc nc nc vcc we nc a17 a14 features ? read access time - 200 ns ? automatic page write operation C internal address and data latches for 256 bytes C internal control timer ? fast write cycle time C page write cycle time - 10 ms maximum C 1 to 256 byte page write operation ? low power dissipation C 80 ma active current ? hardware and software data protection ? data polling for end of write detection ? high reliability cmos technology C endurance: 10,000 cycles C data retention: 10 years ? single 5v 10% supply ? cmos and ttl compatible inputs and outputs ? jedec approved byte-wide pinout description the AT28C040 is a high-performance electrically erasable and programmable read only memory (eeprom). its 4 megabits of memory is organized as 524,288 words by 8 bits. manufactured with atmels advanced nonvolatile cmos technology, the device offers access times to 200 ns with power dissipation of just 440 mw. rev. 0542bC10/98 pin configurations pin name function a0 - a18 addresses ce chip enable oe output enable we write enable i/o0 - i/o7 data inputs/outputs nc no connect side braze, flatpack to p v i e w 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a18 a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd vcc we a17 a14 a13 a8 a9 a11 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 (continued) 4-megabit (512k x 8) paged parallel eeproms AT28C040
AT28C040 2 the AT28C040 is accessed like a static ram for the read or write cycle without the need for external components. the device contains a 256-byte page register to allow writ- ing of up to 256 bytes simultaneously. during a write cycle, the address and 1 to 256 bytes of data are internally latched, freeing the address and data bus for other opera- tions. following the initiation of a write cycle, the device will automatically write the latched data using an internal con- trol timer. the end of a write cycle can be detected by data polling of i/o7. once the end of a write cycle has been detected, a new access for a read or write can begin. atmel's AT28C040 has additional features to ensure high quality and manufacturability. the device utilizes internal error correction for extended endurance and improved data retention characteristics. an optional software data protec- tion mechanism is available to guard against inadvertent writes. the device also includes an extra 256 bytes of eeprom for device identification or tracking. block diagram absolute maximum ratings* temperature under bias................................ -55 c to +125 c *notice: stresses beyond those listed under absolute maximum ratings may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65 c to +150 c all input voltages (including nc pins) with respect to ground ...................................-0.6v to +6.25v all output voltages with respect to ground .............................-0.6v to v cc + 0.6v voltage on oe and a9 with respect to ground ...................................-0.6v to +13.5v
AT28C040 3 device operation read: the AT28C040 is accessed like a static ram. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins is asserted on the outputs. the outputs are put in the high impedance state when either ce or oe is high. this dual- line control gives designers flexibility in preventing bus con- tention in their systems. byte write: a low pulse on the we or ce input with ce or we low (respectively) and oe high initiates a write cycle. the address is latched on the falling edge of ce or we , whichever occurs last. the data is latched by the first rising edge of ce or we . once a byte write has been started, it will automatically time itself to completion. once a pro- gramming operation has been initiated and for the duration of t wc , a read operation will effectively be a polling opera- tion. page write: the page write operation of the AT28C040 allows 1 to 256 bytes of data to be written into the device during a single internal programming period. a page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 255 addi- tional bytes. each successive byte must be written within 150 m s (t blc ) of the previous byte. if the t blc limit is exceeded, the AT28C040 will cease accepting data and commence the internal programming operation. all bytes during a page write operation must reside on the same page as defined by the state of the a8 - a18 inputs. for each we high to low transition during the page write opera- tion, a8 - a18 must be the same. the a0 to a7 inputs specify which bytes within the page are to be written. the bytes may be loaded in any order and may be altered within the same load period. only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. data polling: the AT28C040 features data polling to indicate the end of a write cycle. during a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on i/o7. once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. data polling may begin at anytime during the write cycle. toggle bit: in addition to data polling, the AT28C040 provides another method for determining the end of a write cycle. during the write operation, successive attempts to read data from the device will result in i/o6 toggling between one and zero. once the write has completed, i/o6 will stop toggling and valid data will be read. reading the toggle bit may begin at any time during the write cycle. data protection: if precautions are not taken, inad- vertent writes may occur during transitions of the host sys- tem power supply. atmel has incorporated both hardware and software features that will protect the memory against inadvertent writes. hardware protection: hardware features protect against inadvertent writes to the AT28C040 in the following ways: (a) v cc sense - if v cc is below 3.8v (typical) the write function is inhibited; (b) v cc power-on delay - once v cc has reached 3.8v the device will automatically time out 5 ms (typical) before allowing a write: (c) write inhibit - holding any one of oe low, ce high or we high inhibits write cycles; (d) noise filter - pulses of less than 15 ns (typical) on the we or ce inputs will not initiate a write cycle. software data protection: a software controlled data protection feature has been implemented on the AT28C040. when enabled, the software data protection (sdp), will prevent inadvertent writes. the sdp feature may be enabled or disabled by the user; the AT28C040 is shipped from atmel with sdp disabled. sdp is enabled when the host system issues a series of three write commands; three specific bytes of data are writ- ten to three specific addresses (refer to software data pro- tection algorithm). after writing the 3-byte command sequence and after t wc , the entire AT28C040 will be pro- tected against inadvertent write operations. it should be noted that once protected, the host can still perform a byte or page write to the AT28C040. to do so, the same 3-byte command sequence used to enable sdp must precede the data to be written. once set, sdp will remain active unless the disable com- mand sequence is issued. power transitions do not disable sdp, and sdp will protect the AT28C040 during power-up and power-down conditions. all command sequences must conform to the page write timing specifications. the data in the enable and disable command sequences is not written to the device, and the memory addresses used in the sequence may be written with data in either a byte or page write operation. after setting sdp, any attempt to write to the device without the 3-byte command sequence will start the internal write timers. no data will be written to the device; however, for the duration of t wc , read operations will effectively be poll- ing operations. device identification: an extra 256 bytes of eeprom memory are available to the user for device iden- tification. by raising a9 to 12v 0.5v and using address locations 7ff80h to 7ffffh, the bytes may be written to or read from in the same manner as the regular memory array. optional chip erase mode: the entire device can be erased using a 6-byte software erase code. please see software chip erase application note for details.
AT28C040 4 notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms. dc and ac operating range AT28C040-20 AT28C040-25 operation operation read program read program operating temperature (case) commercial 0c - 70c 0c - 70c 0c - 70c 0c - 70c industrial -40c - 85c -40c - 85c -40c - 85c -40c - 85c extended -55c - 125c -40c - 85c -55c - 125c -40c - 85c v cc power supply 5v 10% 5v 10% 5v 10% 5v 10% operating modes mode ce oe we i/o read v il v il v ih d out write (2) v il v ih v il d in standby/write inhibit v ih x (1) x high z write inhibit x x v ih write inhibit x v il x output disable x v ih x high z dc characteristics symbol parameter condition min max units i li input load current v in = 0v to v cc + 1v 10 m a i lo output leakage current v i/o = 0v to v cc 10 m a i sb1 v cc standby current cmos ce = v cc - 0.3v to v cc + 1v 3 ma i sb2 v cc standby current ttl ce = 2.0v to v cc + 1v 3 ma i cc v cc active current f = 5 mhz; i out = 0 ma 80 ma v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage i ol = 2.1 ma 0.45 v v oh1 output high voltage i oh = -400 m a2.4v v oh2 output high voltage cmos i oh = -100 m a; v cc = 4.5v 4.2 v
AT28C040 5 ac read waveforms (1)(2)(3)(4) note: 1. ce may be delayed up to t acc - t ce after the address transition wihtout impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce , whichever occurs first (c l = 5 pf). 4. this parameter is characterized and is not 100% tested. input test waveforms and measurement level t r , t f < 5 ns output test load note: 1. this parameter is characterized and is not 100% tested. ac read characteristics symbol parameter AT28C040-20 AT28C040-25 units min max min max t acc address to output delay 200 250 ns t ce (1) ce to output delay 200 250 ns t oe (2) oe to output delay 0 55 0 55 ns t df (3)(4) ce or oe to output float 0 55 0 55 ns t oh output hold from oe , ce or address, whichever occurred first 0 0 ns pin capacitance f = 1 mhz, t = 25c (1) symbol typ max units conditions c in 410pfv in = 0v c out 812pfv out = 0v
AT28C040 6 ac write waveforms we controlled ce controlled ac write characteristics symbol parameter min max units t as , t oes address, oe set-up time 0 ns t ah address hold time 50 ns t cs chip select set-up time 0 ns t ch chip select hold time 0 ns t wp write pulse width (we or ce ) 100 ns t ds data set-up time 50 ns t dh , t oeh data, oe hold time 0 ns
AT28C040 7 page mode write waveforms (1)(2) notes: 1. a8 through a18 must specify the page address during each high to low transition of we (or ce ). 2. oe must be high only when we and ce are both low. page mode characteristics symbol parameter min max units t wc write cycle time 10 ms t as address set-up time 0 ns t ah address hold time 50 ns t ds data set-up time 50 ns t dh data hold time 0 ns t wp write pulse width 100 ns t blc byte load cycle time 150 m s t wph write pulse width high 50 ns
AT28C040 8 software data protection enable algorithm (1) notes: 1. data format: i/o7 - i/o0 (hex); address format: a14 - a0 (hex). 2. write protect state will be activated at end of write even if no other data is loaded. 3. write protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 256 bytes of data are loaded. software data protection disable algorithm (1) software protected program cycle waveform (1)(2)(3) notes: 1. a0 - a14 must conform to the addressing sequence for the first 3 bytes as shown above. 2. after the command sequence has been issued and a page write operation follows, the page address inputs (a8 - a18) must be the same for each high to low transition of we (or ce ). 3. oe must be high only when we and ce are both low. load data aa to address 5555 load data 55 to address 2aaa load data a0 to address 5555 load data xx to any address (4) load last byte to last address enter data protect state writes enabled (2) load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 20 to address 5555 load data xx to any address (4) load last byte to last address load data 55 to address 2aaa exit data protect state (3)
AT28C040 9 notes: 1. these parameters are characterized and not 100% tested. 2. see ac read characteristics. data polling waveforms notes: 1. these parameters are characterized and not 100% tested. 2. see ac read characteristics. toggle bit waveforms (1)(2)(3) notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. 2. beginning and ending state of i/o6 will vary. 3. any address location may be used but the address should not vary. data polling characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns toggle bit characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 150 ns t wr write recovery time 0 ns
AT28C040 10 note: 1. see valid part numbers. ordering information (1) t acc (ns) i cc (ma) ordering code package operation range active standby 200 80 3 AT28C040-20bc AT28C040-20fc AT28C040-20lc 32b 32f 44l commercial (0 to 70 c) 80 3 AT28C040-20bi AT28C040-20fi AT28C040-20li 32b 32f 44l industrial (-40 to 85 c) 80 3 AT28C040-20bi sl703 AT28C040-20fi sl703 AT28C040-20li sl703 32b 32f 44l extended (see dc and ac operating range table) 250 80 3 AT28C040-25bc AT28C040-25fc AT28C040-25lc 32b 32f 44l commercial (0 to 70 c) 80 3 AT28C040-25bi AT28C040-25fi AT28C040-25li 32b 32f 44l industrial (-40 to 85 c) 80 3 AT28C040-25bi sl703 AT28C040-25fi sl703 AT28C040-25li sl703 32b 32f 44l extended (see dc and ac operating range table) valid part numbers the following table lists standard atmel products that can be ordered. device numbers speed package and temperature combinations AT28C040 20 bc, bi, fc, fi, lc, li, bi sl703, fi sl703, li sl703 AT28C040 25 bc, bi, fc, fi, lc, li, bi sl703, fi sl703, li sl703 die products reference section: parallel eeprom die products package type 32b 32-lead, 0.600" wide, ceramic side braze dual inline (side braze) 32f 32-lead, non-windowed, ceramic bottom-brazed flat package (flatpack) 44l 44-pad, non-windowed, ceramic leadless chip carrier (lcc) options blank standard device: endurance = 10k write cycles; write time = 10 ms
AT28C040 11 packaging information pin #1 id .370(9.40) .270(6.86) .019(.482) .015(.381) .050(1.27) bsc .045(1.14) max .120(3.05) .098(2.49) .045(1.14) .026(.660) .072(1.82) .030(0.76) .408(10.4) .355(9.02) .006(.152) .004(.101) .488(12.4) .472(12.0) .829(21.1) .811(20.6) *ceramic lid standard unless specified. 32b , 32-lead, 0.600" wide, ceramic side braze dual inline (side braze) dimensions in inches and (millimeters) 32f , 32-lead, non-windowed, ceramic bottom- brazed flat package (flatpack) dimension in inches and (millimeters) jedec outline mo-115 44l , 44-pad, non-windowed, ceramic leadless chip carrier (lcc) dimensions in inches and (millimeters)* mil-std-1835 c-5
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